In modern Integrated Circuit (IC) packaging, multiple dies may be stacked to allow higher levels of integration without increasing the package footprint. The technology is known as three dimensional (3D) vertical packaging, and may involve flip-chip technology or wire bonding of dies in a vertical arrangement. Wire bonding for die interconnection is mostly used over flip-chip technologies for lower signal bandwidth applications, as the infrastructure for flip-chip technology is generally more expensive and complex than wire bonding. One challenge of wire bonding for 3D packaging of dies having the same size is the need to route the interconnecting wires from the individual dies to the substrate and back to the next die when the dies are stacked in a straight-up configuration, that is, when the die edges are all aligned. In such a configuration, the package footprint is approximately the size of the dies themselves. Long wire die-to-die interconnections are required in this case, decreasing signal bandwidth. In the alternative, the die may be stacked in a shingle stack configuration, where the die edges are offset. Here, the wires may be bonded directly between dies, producing short die-to-die interconnects, but the package footprint is increased significantly over the footprint of a straight-up vertical stack having three dies or more in the stack. As demand for low-cost packages having small footprint and high performance is on the rise, there is a drive for improved 3D packaging taking advantage of the current wire bonding infrastructure.